How TCS is Advancing Chiplet Design for AI Infrastructure

As AI adoption accelerates, the semiconductor industry faces pressure to deliver performance, scalability and efficiency at scale. 

In this domain, Tata Consultancy Services (TCS) combines decades of expertise with research partnerships to redefine how chips are designed, built and deployed for the AI era.

Prasad Patchigolla, Vice President (VP) and Chief Technology Officer (CTO) of Technology, Software and Services at TCS, speaks about how the company helps the semiconductor sector overcome the limits of traditional monolithic design.

“My role is to define technology vision, co-create foundational technologies and solutions with industry partners, academia and open-source communities and orchestrate ecosystems to re-imagine the way people live, societies function and Enterprises operate,” he explains.

“At TCS, we are partnering with our customers to pioneer a new era of AI innovation – right from silicon to software. Our collaborative approach ensures that every solution is optimised for performance and scalability, empowering our clients to stay ahead in the competitive landscape.

“At TCS, our philosophy is centred on creating synergy between AI and human intelligence, ensuring that technology amplifies human creativity, drives sustainable value and shapes a more intelligent, connected future.”

What are the biggest technical and economic barriers facing traditional monolithic chip design as AI compute needs continue to soar?

For decades, Moore’s Law – or the doubling of transistor counts on integrated circuit (IC) every two years – guided steady progress in the semiconductor industry, delivering exponential gains in a chips’ performance and efficiency.

However, as industry moves towards two-nanometre transistors and beyond, the drive of traditional monolithic system-on-chip (SoC) model is becoming increasingly complex, costly and difficult to scale. 

Traditional monolithic chips have reached a point where each new generation requires significant investment in design and fabrication. Packing billions of transistors onto a single large die results in plummeting yields and therefore higher costs. 

For companies racing to deliver new AI devices, this model is unsustainable. Chiplets can address this problem by breaking large designs into smaller modules, reducing the die size resulting in drastically higher yields. 

How do chiplet-based architecture specifically address the scalability demands of AI and Gen AI workloads that current chips struggle with?

Industry is being reshaped by relentless demand for processing power, driven in part by AI and Gen AI technology, challenging the limits of computing performance available to meet the needs of the AI era. 

The answer to this challenge is chiplets. 

Chiplets offer a substitution to massive integrated circuits in favor of smaller, modular dies, each optimised for a specific function and integrated into a larger system package. 

Chiplets can either be reused or designed, validated and fabricated independently on different technological nodes, cutting both development time and expense while lowering risk. 

As these smaller chiplets allow heterogeneous integration, they are easier to test and optimise individually, hence reducing the burden of verification, while allowing proven components to be repurposed across multiple designs.

This technology can accelerate semiconductor innovation by addressing the problems of cost and flexibility, efficiency and scalability needed to fuel AI’s next phase of growth.

In launching TCS’ Chiplet-based System Engineering Services, how do you see this shaping semiconductor companies’ ability to shorten time to market while lowering design costs?

TCS Chiplet-based System Engineering Services are designed to help semiconductor companies push the boundaries of traditional chip design. 

By reusing validated modules and customising packages, chipmakers can shorten innovation cycles, reduce risk, increase yield and lower costs, and bring intelligence to every device and system that needs it.

By breaking down complex designs into smaller modules that can be designed, validated and reused independently, we significantly cut development time and expense, lowering risk compared to building monolithic chips from scratch. 

This allows clients to launch new chips faster at a reduced design cost.

Using chiplets, we can also accelerate design cycles by leveraging validated modules and connecting them with standardised interfaces.

At TCS, we support our clients by designing and verifying these critical interconnects and advanced packages, including addressing challenges like heat dissipation in 3D stacking, enabling greater flexibility, scalability and cost-efficiency, which are vital for the rapid pace of the AI revolution. 

This approach transforms how AI scales up, allowing for the rapid creation of custom chips for diverse applications.

Strides have already been made to help semiconductor firms in transitioning to this new paradigm. 

For instance, TCS recently collaborated with a major North American semiconductor firm to streamline the integration of chiplets into a single package, effectively addressing challenges related to heterogeneous device integration. 

By adopting modern chiplet-based design methodologies, TCS is enabling its partner to accelerate the delivery of industry-leading AI processors and bring them to market more rapidly.

With interconnect performance often cited as a major challenge, what breakthroughs or industry-wide standards are most critical to unlocking chiplets’ full potential?

Interconnect performance is absolutely crucial for chiplets – it's the backbone of this new architecture. 

Before, when everything resided on a single silicon die, communication wasn't a bottleneck. But now that components are in one package, robust, high-speed connectivity is essential.

Due to the data-intensive nature of AI workloads, the interface between processors and memory represents the performance bottleneck when connected via a Printed Circuit Board (PCB). 

Integrating processors and memory as chiplets within a single package helps mitigate this limitation. This approach forms the basis for High-Bandwidth Memory (HBM), which has become prevalent in devices designed for AI applications.

Key breakthroughs and industry standards like UCIe™ (Universal Chiplet Interconnect Express) are critical, providing a standardised, high-bandwidth, low-latency interface for seamless chiplet integration regardless of the manufacturer. 

This allows different modules, potentially from different vendors, to communicate effectively and efficiently.

Alongside this, advancements in high-bandwidth memory (HBM) integration are vital, as memory bandwidth and data transfer rates become as critical as raw compute for large AI models. 

Furthermore, packaging innovations like 2.5D and 3D stacking, while introducing challenges like thermal management, are essential for creating denser, more efficient systems. 

TCS actively designs and verifies these interconnects and advanced packages, helping to create the unified, high-performance systems needed to overcome the limitations of monolithic designs.

Looking ahead, how will chiplet architectures and advanced packaging techniques influence the development of highly specialised AI chips for diverse applications, from hyperscale data centres to edge devices?

Looking ahead, we see chiplet architectures and advanced packaging techniques profoundly influencing the development of highly specialised AI chips by enabling a ‘fit-for-purpose’ design philosophy. 

This will allow chipmakers to rapidly create custom solutions for incredibly diverse applications, from hyperscale data centres training the largest models to tiny edge devices like robots, autonomous vehicles, smart appliances or industrial machinery with embedded intelligence. 

The introduction of chiplets offers more than just a workaround to Moore’s Law – they provide a means for the semiconductor industry to meet the unique demands of the AI age.

Chiplet-based system engineering can be the foundation of semiconductor design going forward and with that an architecture that ensures AI can scale sustainably across industries.

The path forward is clear: sustaining the next wave of AI will require more than incremental scaling of existing systems. It calls for rethinking semiconductor design at a fundamental level.

Chiplets provide that foundation, enabling architecture that can meet the evolving demands of AI across every sector.