Huawei Unveils Tau Scaling Law for Next-Gen Chip Evolution

Rapid breakthroughs in computing mean the semiconductor industry can no longer rely on Moore’s Law as transistors approach atomic limits. While this principle guided the industry for more than five decades, it now faces severe physical constraints and diminishing economic returns. 

Huawei has unveiled the Tau Scaling Law to overcome these physical constraints, ushering in a new principle for chip-making. It shifts the focus from shrinking transistors to cutting signal transmission times through chips and computing systems. 

Based on this principle, the company is developing innovative core technologies like LogicFolding, which is a methodology that transitions chip architecture from traditional two-dimensional grids to three-dimensional layouts. 

The result is a multi-level co-optimisation mechanism that spans semiconductor devices, circuits, chips and systems, shortening data travel times and driving up speed and energy efficiency.

The new development was revealed in a keynote speech delivered by He Tingbo, Co-President of Huawei, at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, China. 

The principle is also referred to as Her's Law, named after Tingbo by her peers and colleagues. 

Moving chip architecture from 2D to 3D 

The presentation introduced the Tau (τ) Scaling Law, which is a paradigm-shifting principle poised to guide the future of the semiconductor industry. Central to this new architectural philosophy is the LogicFolding methodology. 

In the past, engineers designed microchips in two dimensions with all components mapped out across a flat, grid-like plane. This traditional layout forces signals to travel longer lateral distances, which creates severe data bottlenecks. 

LogicFolding fundamentally breaks these physical boundaries by transitioning chip architecture to a 3D design. Instead of spreading components out horizontally, LogicFolding layers multiple 2D planar circuits directly on top of each other.

The mechanism works like moving from a single-story home to a multi-story building where people move between floors quickly using elevators. This vertical stacking creates room for more transistors and places core circuits closer together.

Shortening the time needed to transmit information between circuits is crucial because transmission time is the primary indicator of frequency and performance. 

By folding the logic layout, the resistive and capacitive load of signal propagation drops dramatically, unlocking new dimensions of computational speed.

Time constant compression across four distinct levels

The multi-level co-optimisation mechanism systematically shortens the time constant τ at every layer of the technology stack:

• At the device level: The company is optimising the resistance and parasitic capacitance of transistors and interconnects, minimising the time constant τ at the underlying physical layer
• At the circuit level: The LogicFolding architecture shortens critical-path wiring and reduces the resistive and capacitive load of signal propagation, boosting both transistor density and circuit performance
• At the chip level: Huawei employs full-stack coordinated design of software, architecture and silicon to achieve fine-grained, workload-driven control over instruction and data flows, which enhances system-level parallelism
• At the system level: The company is redefining interconnect protocols for computing systems with UnifiedBus to achieve unified memory addressing and native memory semantics for SuperPoDs, significantly reducing system communications latency.

LogicFolding for next-gen smartphones

Tingbo elaborated on the application of the τ Scaling Law to smartphones and AI computing during the keynote speech. 

Over the past six years, Huawei has designed and mass-produced 381 chips based on the τ Scaling Law to serve a wide range of industries, sectors and markets.

The Kirin chips scheduled to launch in autumn 2026 will be the first ever to adopt the LogicFolding architecture. This commercial launch will considerably enhance the performance of the chips in consumer devices.

By 2031, the high-end chips that Huawei designs based on the τ Scaling Law are expected to feature a transistor density that is equivalent to 14 Å processes, which represents a 1.4 nm scale.

This roadmap charts a clear course for next-generation smartphones and heavy-duty AI computing infrastructure.

With the τ Scaling Law, Huawei looks forward to working closely with scientists, engineers and industry partners around the world to drive the sustainable development of the electronics industry. 

Tingbo notes, “We believe that openness and collaboration are key to driving ongoing progress in the semiconductor industry. No single company can independently find all the answers along the path of semiconductor evolution.”